Detailed JD :

• Proficiency in analog layout design, specifically at lower technology nodes.
• Extensive experience with FinFET technologies.
• Skilled in designing and laying out Phase-Locked Loops (PLL).
• Expertise in Transmitter (Tx) and Receiver (Rx) layouts.
• Strong understanding of layout techniques for analog and mixed-signal circuits.
• Knowledgeable in managing the challenges associated with lower node geometries.
• Capable of optimizing analog layouts for performance, power, and area (PPA).
• Proficient in using EDA tools for analog layout design.
• Familiarity with parasitic extraction and minimizing parasitic effects in layouts.
• Understanding of electromigration and IR drop considerations in analog design.
• Ability to perform layout versus schematic (LVS) and design rule check (DRC) verification.
• Excellent attention to detail and ability to ensure high-quality, manufacturable layouts.
• Strong collaboration skills to work effectively with circuit design and verification teams.

Must to have :

• Lower Nodes, Finfet Technologies,  PLL, Tx, and Rx Layouts.